Question:

1. Consider three processors with different cache configurations: 
Cache 1: Direct-mapped with one-word blocks 
Cache 2: Direct-mapped with four-word blocks
Cache 3: Two-way set associative with four-word blocks

The following miss rate measurements have been made:

Cache 1: Instruction miss rate is 4%; data miss rate is 6%
Cache 2: Instruction miss rate is 2%; data miss rate is 4%
Cache 3: Instruction miss rate is 2%; data miss rate is 3%

For these processors, one-half of the instructions contain a data reference. Assume that the cache miss penalty is 6 + Block size in words. The CPI for this workload was measured on a processor with cache 1 and was found to be 2.0. Determine which processor spends the most cycles on cache misses. 

2. Programming Problem: [30 points]A system comprises of a set-associative cache and main memory. A cache hit occurs whenever a memory access is found in the cache. In case of a miss the data is fetched from the main memory. Only one clock cycle is required to access data from the cache, whereas 99 clock cycles are required for fetching data from the main memory. For simplicity, assume that the cache size is fixed and equals 8 blocks, where length of a block is equal to 1 word. Also assume that the memory structure comprises of 32 words. Assume no hazards. 

The ISA on the system has 4 different instructions A, B, C and L, of which only the L-type instruction references memory. The syntax of L-type instruction is <L memory-address>

In the language of your choice simulate the working of the above set-associative cache for an arbitrary memory access sequence, and indicate the total cache hits,misses and the total cycle time.

Your program should take as input
1. The set size (in number of blocks).
2. The trace file containing an arbitrary combination of instructions A, B, C andL.

Your program should output
1. Total clock cycles.
2. Total number of hits and misses.

Use Least Recently Used (LRU) as the block replacement strategy.
For example:
For Set Size = 2 and the following trace file
A
L 0
L 8
L 0
B
C
L 12
A
L 6
B
L 8
C
Total clock-cycle=502, number of hits =1, number of misses = 5