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Elementary,Middle School,High School,College,University,PHD
Teaching Since: | May 2017 |
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MBA (IT), PHD
Kaplan University
Apr-2009 - Mar-2014
Professor
University of Santo Tomas
Aug-2006 - Present
Assignment 7
G(s) = K / (s(s + 10)(s +50))
We want the overshoot to be approximately 7.5% for a step input and the settling time (with a 2% criterion) of the system be 400ms. Find a suitable phase-lead compensator by using root locus methods. Let the zero of the compensator be located at s = -15, and determine the compensator pole. Determine resulting Kv.
We desire the steady-state error to a step input to be approximately 5% and the phase margin of the system to be approximately 45 degrees. Design a lag network to meet these specifications.
Lab 7
The Design of Feedback Control Systems
Assignment 8
Digital Control Systems
Gp(s) = 2 / (s + 2)
G(z) = K (z3 + 10.3614z2 + 9.758z + 0.8353) / (z4 – 3.7123z3 + 5.1644z2 – 3.195z + 0.7408)
Lab 8
Digital Control Systems
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