Shown below is a VLIW system in which each long instruction word generated by the compiler is a packet or bundle of three individual machine operations. The hardware system contains two integer units and one floating point unit. Therefore, up to 2 integer operations and 1 floating point operation can be performed in parallel in the same clock cycle. However, due to the mix of available instructions and possible dependencies, the system may not be able to make use of all the execution units for a particular cycle. In that case, the compiler would insert one or more nops into the instruction bundle (i.e., into the long instruction word) to fill any unused slots.
(5) Show the contents of the long instruction words or bundles that the compiler would generate for the following group of instructions:
add      $11,$2,$3
add      $4,$5,$11
sub.s    $f14,$f16,$f18
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(5) Show the contents of the long instruction words or bundles that the compiler would generate for the following group of instructions:
add         $11,$2,$3
add.s       $f4,$f5,$f6
sub.s       $f14,$f16,$f1
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Posted 18 May 2017 02:05 AM
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