Q1.  Draw the circuit diagram of a full adder made up of two half-adders

             Write complete VHDL code for the full adder in structural style

             assuming the required components are available in the work library.

             Use IEEE std-logic type for the ports

     Q2.   (i)  Develop the truth table for a 4 X 2 priority encoder. Assume the input as

                   X(3 downto 0)  and the output as Y(1 downto 0) both being bit vectors           

              (ii) Draw K-maps separately for Y(1) and Y(0)

              (ii) From the K-maps, derive Boolean equations for the outputs Y(1) and Y(0)

                     in terms of the inputs X(3), X(2), X(1) and X(0)

              (iii) Write complete VHDL code (entity and architecture) in behavioral

                     style or dataflow style.

              (Note: The inputs cannot be all zeroes)

     Q3   (a)   

 (i) Declare an array of dimension 5 each of whose elements is a positive

      integer

(ii) Declare a type consisting of floating point numbers between -5.5 and +3.8

(iii)Declare a character string and initialize it to “STOPPED ON ERROR”

(iv) Evaluate “100011”  sra  2

(v)  Evaluate    (- 37) rem (-11)

 (b)

            State whether the following are true or false:

 (i)   “01010”  < =   “01001”

(ii)   “ABC” > “AbC”

             (iii)  A nor not B is an illegal expression  in VHDL

             (iv)  VOLT is a  predefined physical type in VHDL

(v)   ‘or’ is distributive over ‘and’

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Status NEW Posted 18 May 2017 06:05 AM My Price 9.00

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