Please help me on Lab problem of Digital Circuit design? 

1. Implement the following functions given below using a single ROM coded in Verilog:

F( x, y , z) = Majority(x, y, z)

 

What is the size of the ROM? What is the truth table for the majority gate? Implement the circuit in behavioral
Verilog and simulate it in ISIM. Remember to use a test bench and top level circuit. After proving that your
unit under test is properly designed, synthesize the circuit in the Xilinx environment. 

-Please show code and simulation results ;  2) show board test results

 

2. Design a positive triggered D-type flip-flop (activated on the rising edge of the clock) out of gates. This means
you must write a structural Verilog description of the flip-flop.

The ISIM simulator will fail to simulate the circuit. What must you add to get the simulator to
initialize properly? Prove to the TA that the circuit works as a divide by two counter using an oscilloscope.
Use the internal oscillator and the function generator as the stimulus. Hint: The interface to the board can
be achieved using the any of the four 6-pin peripheral module connectors such as PIN B2 signal JA1. The
internal clock can be reference using PIN B8 signal MCLK.

-Please show code and simulation results

 

3. Connect the flip-flop you have already designed to create a divide by two counter. Use structural Verilog.

-Please show code and simulation results