(25 points) Dynamic Scheduling. The following stream of instructions is executed on a

processor that supports Tomasulo’s algorithm (with reservation stations and without reorder

buffer).

L.D F1, 8(R1) ; F1 = MEM[R1+8]

L.D F2, 8(R2) ; F2 = MEM[R2+8]

MUL.D F4, F1, F2 ; F4=F1*F2

S.D F4, 8(R2) ; MEM[R2+8] = F4

ADD.D F4, F1, F2 ; F4 = F1+F2

ADD.D F6, F6, F4 ; F6 = F6+F4

(a) Please list the number of dependences in the code including RAW, WAW and WAR.

(b) Based on the example from Figure 3.7 in the textbook, show what the information tables

look like when only the first load has completed and written its result F1. Be sure to

include three tables for instruction status, reservation stations and register status.

(c) Then show what the information tables look like when the MUL.D instruction is ready to

write its result F4. Be sure to include three tables for instruction status, reservation

stations and register status.

 

CDA 5155 – Homework #3Submission:1.An email submission with a word or PDF document to the instructor (yuw@cs.fsu.edu).Due Date:1.Thursday, April 7th, 2016, 11:50pm for all studentsLate Penalty:1.10% per day (5% if within 3 hours).2.Maximum two daysQuestions:1.(25 points)Dynamic Scheduling. The following stream of instructions is executed on aprocessor that supports Tomasulo’s algorithm (with reservation stations and without reorderbuffer).L.DF1, 8(R1); F1 = MEM[R1+8]L.DF2, 8(R2); F2 = MEM[R2+8]MUL.DF4, F1, F2; F4=F1*F2S.DF4, 8(R2); MEM[R2+8] = F4ADD.DF4, F1, F2; F4 = F1+F2ADD.DF6, F6, F4; F6 = F6+F4(a)Please list the number of dependences in the code including RAW, WAW and WAR.(b)Based on the example from Figure 3.7 in the textbook, show what the information tableslook like when only the first load has completed and written its result F1. Be sure toinclude three tables for instruction status, reservation stations and register status.(c)Then show what the information tables look like when the MUL.D instruction is ready towrite its result F4. Be sure to include three tables for instruction status, reservationstations and register status.(d)Finally, assume that the execution of instructions take one cycle for integer ALUoperation, 2 cycles for Load/Stores (one for address calculation; another for data access),2 cycles for ADD.D, and 4 cycles for MUL.D. Fill in the following table for theexecution timing (in terms of cycle) of all instructions.InstructionIssue atExecutestart atExecuteend atData atWriteCDB atL.DF1, 8(R1)12234L.DF2, 8(R2)MUL.DF4, F1, F2S.DF4, 8(R2)ADD.DF4, F1, F2ADD.DF6, F6, F42.(25 points)Speculative Tomasulo and Speculative Superscalar. The following loop ofinstructions is executed. Assume that the execution takes one cycle for integer ALUoperations and branches, 2 cycles for Load/Stores (one for address calculation; another fordata access), 2 cycles for ADD.D, and 4 cycles for MUL.D.LOOP:L.DF2, 8(R2); F2 = MEM[R2+8]MUL.DF4, F2, F2; F4=F2*F2S.DF4, 8(R2); MEM[R2+8] = F4ADD.DF4, F2, F2; F4 = F2+F2ADD.DF6, F6, F4; F6 = F6+F4DSUBUI R4, R4, #8; R4 = R4 - 8BNEQR4, LOOP; if R4 != 0, jump to LOOP

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