I have finished this project, but I need someone help me to optimize it, e.g. combine two alu files in one alu file, change the memory design. I can do it by myself, however, i need to finish it today and i am busy with other things. I really need someone to help me!! and I suggest you can use the ModelSim software to make it!

Thank you!

 

Problem 2
Design and Implementation of a MIPS CPU with Multicycle Datapath
DATAPATH 1. INTRODUCTION
In this problem, you will design a custom RISC processor which is basically a
stripped down MIPS processor. The goal of this problem is to provide you with a
more practical hands-on approach to computer architecture design problems. The
processor you will be designing is a 32-bit version of the MIPS processor; however,
the instruction set will be a small subset of the actual MIPS ISA. You should
implement the multicycle datapath version of the processor utilizing the VHDL
hardware descriptive language. You may use any constructs within the VHDL
language. The processor supports the three instruction formats: R-format, I-format, and J-format
as described in the text book and lectures. Table I Summarizes the core set of
instructions for your ISA. The memory is assumed to be word addressable and each
word is 32 bits.
Table I: Core MIPS Instruction Set to be Designed (with example)
OpCode
[31 : 26]
100011
101011
000000
000100 Function Field
[5 : 0]
--100000
-- Instruction Operation lw
sw
add
bne
(Custom set) lw $s3, 300($t2)
sw $t6, 400($s7)
add $s5, $t3, $t1
beq $s6, $t5, 200 The total set you need to design is the core set as above + a custom set
designated for you as follows.
BEQ, ORI 2. Implementation Details
Your goal is to get the instruction set implemented and tested. This problem 2 will
focus on the implementation of the datapath without the control design. Once the
datapath is assembled, write a test bench or simulation script to test each instruction
(e.g., with the examples given in Table I). If you work with abstraction in mind by
first testing each lower part completely, it will eliminate potential errors within
your design later.
Datapath Components
ALU implementation can be done similar to the example described in the text book.
You can start with a 1-bit ALU cell and construct a 32-bit ALU unit. Note that you
may have to modify the existing 1-bit cell design to provide more functions due to
extended ISA in your CPU design.
3. Report
You are required to turn in a report that describes the design along with the VHDL
code. The report should be typed, well written, and well organized. The suggested
contents of the report are as follows:
• An overview of your design
• Appropriate sections to convey your report
• A discussion on how you tried to optimize your design
• A discussion on any improvements or additional features made to your design
• A discussion on what does not work correctly in your design
• An overview block diagram of your design. In order to draw this
appropriately, you will have to understand the multi cycle MIPS code and its
operation
• A sample simulation of your design that is annotated to show its correct
operation.

• 1495589811-vhal_code_files.zip
• 1495589813-problem2 - en.pdf

ComputerScienceExpert

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Status NEW Posted 24 May 2017 01:05 AM My Price 9.00

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