ComputerScienceExpert

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About ComputerScienceExpert

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Expertise:
Applied Sciences,Calculus See all
Applied Sciences,Calculus,Chemistry,Computer Science,Environmental science,Information Systems,Science Hide all
Teaching Since: Apr 2017
Last Sign in: 103 Weeks Ago, 2 Days Ago
Questions Answered: 4870
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Education

  • MBA IT, Mater in Science and Technology
    Devry
    Jul-1996 - Jul-2000

Experience

  • Professor
    Devry University
    Mar-2010 - Oct-2016

Category > Programming Posted 26 Apr 2017 My Price 8.00

implement a processor’s datapath

  • (chapter 4.3) Assume that the logic blocks needed to implement a processor’s datapath have the following latencies:

I-Mem

Add

Mux

ALU

Regs

D-Mem

Sign-Extend

Shift-Left-2

200ps

70ps

20ps

90ps

90ps

250ps

15ps

10ps
  • If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? (2 point)
  • Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would be the cycle time for this datapath? (2 points).
  • Repeat part b), but this time we need to support only conditional PC-Relative branches. (2 points)
  • Which kind of instructions require datapath element Shift-Left-2? (2 points).
  • Assume that we only support beq and add instructions, discuss how changes in the given latency of shift-Left-2 affect the cycle time of the processor. Assume that the latencies of other resources do not change. (2 points)

Answers

ComputerScienceExpert
(11)
Status NEW Posted 26 Apr 2017 07:04 AM My Price 8.00

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