14.30 Repeat Example 14.3 for a pseudo-NMOS inverter fabricated in a 0.13-μm CMOS technology for which VDD = 1.2 V, |Vt |= 0.4 V, kn/kp =5, and kn =500 μA/V2. Find VOH, VOL, IDD, and the average power dissipation Pav. Also, use the expression given in Exercise 14.5 to evaluate VM.

Example 14.3  To eliminate the problem associated with the need for a large resistance RD in the circuit of Fig. 14.20

(a), studied in Example 14.2, RD can be replaced by a MOSFET. One such possibility is the circuit in Fig.  4.21, where the load is a PMOS transistor QP whose gate is tied to ground in order to turn it on. Because of its resemblance to an earlier form of logic (NMOS logic, now obsolete) in which the load is an NMOS transistor, this circuit is known as a pseudo-NMOS inverter. (a) Assuming λ1 = λ2 = 0, Vtn  =−Vtp = Vt , and kn = 5kp, find VOH and VOL.

 (b) For kn = 300 μA/V2, Vt = 0.4 V, and VDD = 1.8 V, evaluate the values of VOH and VOL and find the average power dissipated in the inverter, assuming it spends half the time in each of its