Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Computer Science Posted 14 Sep 2017 My Price 5.00

memory system

Consider a memory system with a level 1 cache of 32 KB and DRAM of 512 MB with the processor operating at 1 GHz. The latency to L1 cache is one cycle and the latency to DRAM is 100 cycles. In each memory cycle, the processor fetches four words (cache line size is four words).

Now consider the problem of multiplying a dense matrix with a vector using a twoloop dot-product formulation. The matrix is of dimension 4K x 4K. (Each row of the matrix takes 16 KB of storage.) What is the peak achievable performance of this technique using a two-loop dot-product based matrix-vector product?
1 /* matrix-vector product loop */
2 for (i = 0; i < dim; i++)
3 for (j = 0; i < dim; j++)
4 c[i] += a[i][j] * b[j];

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Maurice Tutor
(5)
Status NEW Posted 14 Sep 2017 07:09 PM My Price 5.00

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