Maurice Tutor

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Category > Computer Science Posted 14 Sep 2017 My Price 9.00

memory in words

1. (20 pts) Suppose we have the following cache:

Set#

Tag

L3:W1

L3:W0

Tag

L2:W1

L2:W0

Tag

L1:W1

L1:W0

Tag

L0:W1

L0:W0

0

0011

A1

A0

0001

K1

K0

0111

M1

M0

      

1

1101

B1

B0

0001

N1

N0

1110

P1

P0

      

2

                        

3

1110

C1

C0

1101

D1

D0

            

4

1110

E1

E0

1010

Q1

Q0

1011

R1

R0

0111

F1

F0

5

                        

6

0100

H1

H0

1010

S1

S0

0111

T1

T0

0101

J1

J0

7

0001

G1

G0

0101

U1

U0

0011

V1

V0

1001

Y1

Y0

The columns labeled Li:Wj contain the jth data word for line Li (e.g., L1:W0 contains the 0th word in the 1st line). The cache policies are:

Replacement: random Write allocate: bypass-cache.

Write update: write-through.

(a) [4 pts] What is the address of the following data words found in the cache above?

Data word

Address

E1

  

D0

  

P0

  

T1

  

(b) [7 pts] Suppose the addresses in the following trace are accessed in order, possibly changing the cache on each access. The R/W column indicates whether the access was a read or a write access. For each access, determine (1) which set in the cache would be accessed to look for the addressed data, (2) does the cache access for this address access result in a hit or a miss? (3) if there is a miss, what type of miss is it? Assume that if the addresses do not appear in the cache above, the addresses have not been accessed before the start of this trace. Be sure your answer is consistent with the cache's policies, listed above.

R/W

Address

Set #

Hit/Miss?

Conflict Miss?

Capacity Miss?

Compulsory Miss?

Read

11100110

          

Write

11110011

          

Read

11110010

          

Write

11110011

          

Read

00000010

          

[4 points] What is the size of the physical (main) memory in words?

[5 points] Suppose the cache access time is 10ns and main memory access time is 75ns/word. What is the

maximum number of misses out of 1000 total accesses that this cache memory system can have before it exceeds an effective access time of 30ns?

Answers

Maurice Tutor
(5)
Status NEW Posted 14 Sep 2017 10:09 PM My Price 9.00

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