Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Computer Science Posted 14 Sep 2017 My Price 4.00

Lw Instruction

problem3

You are to examine how pipelining affects the clock cycle time of the processor.please assume that individual stages of the datapath have following latencies:

IF              ID                 EX                  MEM                   WB

250PS     350PS          150PS             300PS                  200PS

a.)What is clock cycle time of the pipeline?

b.)what is the total latency of an Lw Instruction?

c.)If we can split one stage of the pipelined data path into two new stages,each with half the latency of the original state,which stage would you split and that is the new clock cycle time of the processor?

Answers

Maurice Tutor
(5)
Status NEW Posted 14 Sep 2017 11:09 PM My Price 4.00

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