1. Figure 5.12 shows the bit fields assigned to register addresses for different groups of instructions. Why is it important to use the same field locations for all instructions? (Picture is attached)

 

2. We have seen how all RISC-style instructions can be executed using the steps in Figure 5.4 on the multi-stage hardware of Figure 5.8. Autoincrement and Autodecrement addressing modes are not included in RISC-style instruction sets. Explain why the instruction Load R3, (R5)+ cannot be executed on the hardware in Figure 5.8.

Show transcribed image text 1. Figure 5.12 shows the bit fields assigned to register addresses for different groups of instructions. Why is it important to use the same field locations for all instructions? (Picture is attached) 2. We have seen how all RISC-style instructions can be executed using the steps in Figure 5.4 on the multi-stage hardware of Figure 5.8. Autoincrement and Autodecrement addressing modes are not included in RISC-style instruction sets. Explain why the instruction Load R3, (R5)+ cannot be executed on the hardware in Figure 5.8. Step Action 1 Fetch an instruction anti increment the program counter. 2 Decode the instruction and read registers from the register file 3 Perform an ALU operation. 4 Read or write memory data if the instruction involves a memory operand. 5 Write the result into the destination register, if needed. Figure 5.4 A five ?step sequence of actions to fatch and execute an instruction