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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
a. Draw a transistor-level diagram for a three-input AND gate and a three-input OR gate. Do this by extending the designs from Figures 3.6a and 3.7a.
b. Replace the transistors in your diagrams from part a with either a wire or no wire to reflect the circuit's operation when the following inputs are applied.
(1) A = l, B = 0,C = 0
(2) A = 0, B=0 , C= 0
(3) A = 1,J? = 1,C = 1
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