Levels Tought:
University
Teaching Since: | Apr 2017 |
Last Sign in: | 345 Weeks Ago, 3 Days Ago |
Questions Answered: | 9562 |
Tutorials Posted: | 9559 |
bachelor in business administration
Polytechnic State University Sanluis
Jan-2006 - Nov-2010
CPA
Polytechnic State University
Jan-2012 - Nov-2016
Professor
Harvard Square Academy (HS2)
Mar-2012 - Present
Â
1. Write a line of HDL code that gates a 32-bit bus called data with another signal called sel to produce a 32-bit result. If sel is TRUE, result = data. Otherwise, result should be all 0’s.
2. Explain the difference between blocking and nonblocking assignments in SystemVerilog. Give examples.
3. What does the following SystemVerilog statement do? result = | (data[15:0] & 16'hC820);
Â
-----------