Maurice Tutor

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  • MCS,PHD
    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 10 Oct 2017 My Price 5.00

adjacent bits

Find the best width and spacing to minimize the RC delay of a metal2 bus in the 180 nm process described in Figure 6.12 if the pitch cannot exceed 960 nm. Minimum width and spacing are 320 nm. First, assume that neither adjacent bit is switching. How does your answer change if the adjacent bits may be switching?

 

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Maurice Tutor
(5)
Status NEW Posted 10 Oct 2017 09:10 PM My Price 5.00

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