Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 13 Oct 2017 My Price 3.00

buffer design problem

Consider the buffer design problem from Example 4.14. If the delay constraint is 20 Y, how many stages will give the lowest energy, and how should the stages be sized?

 

Example 4.14

A control unit generates a signal from a unit-sized inverter. The signal must drive unit-sized loads in each bitslice of a 64-bit datapath. The designer can add inverters to buffer the signal to drive the large load. Assuming polarity of the signal does not matter, what is the best number of inverters to add and what delay can be achieved?

 

 

 
 

Answers

Maurice Tutor
(5)
Status NEW Posted 13 Oct 2017 12:10 PM My Price 3.00

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