Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 16 Oct 2017 My Price 3.00

BCD counter

Design a MOD-100, BCD counter using either two 74HC160 or two 74HC162 chips and any necessary gates. The IC counter chips are to be synchronously cascaded together to produce the BCD count sequence for 0 to 99. The MOD-100 is to have two control inputs, an active-HIGH count enable (EN) and an active-HIGH, synchronous load (LD). Label the counter outputs Q0, Q1, Q2, etc., with Q0 LSB. Which set of outputs represents the 10s digit?

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Maurice Tutor
(5)
Status NEW Posted 16 Oct 2017 02:10 PM My Price 3.00

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