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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
B.50  Assume that a gate array exists in which the logic cell used is a three-input NAND gate. The inputs to each NAND gate can be connected to either 1 or 0, or to any logic signal. Show how the following logic functions can be realized in the gate array. (Hint: Use DeMorgan’s theorem.)
(a) f = x1x2 + x3                                           Â
(b) f = x1x2x4 + x2x3x4 + x1
B.51Â Â What logic gate is realized by the circuit in Figure PB.10? Does this circuit suffer from any major drawbacks?
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Figure PB.10Â Â Â Â Â Circuit for Problem B.51.
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*B.52Â What logic gate is realized by the circuit in Figure PB.11? Does this circuit suffer from any major drawbacks?
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Figure PB.11Â Circuit for Problem B.52.
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