Maurice Tutor

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  • MCS,PHD
    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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  • Professor
    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 02 Nov 2017 My Price 3.00

noncritical inputs


1. Design an asymmetric 3-input NOR gate that favors a critical input over the other two. Choose transistor sizes so the logical effort on the critical input is 1.5. What is the logical effort of the noncritical inputs?

 

2. Many standard cell libraries choose a P/N ratio for an inverter in between that which would give equal rising and falling delays and that which would give minimum average delay. Why is this done?

 

Answers

Maurice Tutor
(5)
Status NEW Posted 02 Nov 2017 07:11 PM My Price 3.00

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