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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, IO_L-17 _L, where IO_L has the highest priority. The circuit should produce active-high address outputs A2-AO to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to name all signals with the proper active levels. This circuit can be built with a single 74xl48 and no other gates.
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