2. Develop a model for the read time of a ROM with 2n rows and 2m columns analogous to that of the SRAM from Section 12.2.6. Assume the wire capacitance in the ROM array is negligible compared to the gate and diffusion capacitance. Assume the ROM cells are laid out such that two cells share a single diffusion contact and hence each contributes only C/2 of diffusion capacitance.