1 A virtual machine is a hypothetical computer whic

h:

a) can never be implemented

b) has a machine language which is not well define

d

c) has a machine language which can be translated

or interpreted

d) is the basic idea behind the Pentium 4 and Core

Series

e) contains a BLU

 

2. Hardware and software:

a) are logically different

b) cannot be converted from one to another

c) are made up of logic gates

d) are logically equivalent

e) are not needed in a virtual machine

 

3. The von Neumann architecture:

a) is still used today

b) in not used today

c) was implemented in first computer designed by E

ckert

d) did not used the concept of stored program

e) had hardwired programs

 

4. The Program Counter register:

a) is located in the Data Path

b) points to the next instruction

c) holds the next instruction

d) receives the result of the ALU computation

e) is always incremented by 1

 

5. Which is not a general design goal of RISC comp

uters:

a) instructions should be easy to decode

b) maximize rate at which instructions are issued

c) direct hardware execution of instructions

d) minimize number of registers on the chip

e) maximize pipelining

 

6. Array processors general use:

a) only one CPU with multiple stages

b) many processors connected in an irregular fashi

on

c) many processors connected together with one bus

d) many processors connected in a geometric patter

n

e) one CPU connected via the Internet

 

7. Each memory location has a label called:

a) a cell

b) a bit ordering

c) an address

d) a binary coded decimal

e) a variable length encoding

 

8. Hamming codes are used for:

a) just error detection

b) error retransmission

c) error detection and correction

d) computing parity of a word

e) minimizing word transmission length

 

9. RAID is used:

a) as a memory speed-up mechanism

b) as a tape backup policy

c) as a safer way to store data on physical disks

d) as a way to compute checksums

e) to decrease the number of physical disks in a s

ystem

 

10. In logic circuits, an inverter is used to:

a) transform voltages to AC

b) OR two values together

c) transform a logic value into its complement

d) buffer a logic value

e) add two integers together

 

11. The formal algebra used to describe the behavi

or of logic circuits is called:

a) Lie algebra

b) XOR algebra

c) truth table algebra

d) Boolean algebra

e) DeMorgan's algebra

 

12. A multiplexer connects:

a) logic outputs to other logic outputs

b) the CPU to the datapath

c) many inputs to one output

d) inverters to inverters

e) one input to many outputs

 

13. The Arithmetic Logic Unit (ALU) is used:

a) to control the external buses

b) issue microinstructions to hardware

c) to perform arithmetic and logical operations on

operands

d) to produce clock signals for the CPU

e) as a memory device

 

14. NAND and NOR gates can be considered to be:

a) useful gates, but other gates types are more im

portant

b) the building blocks of all other gate types

c) never integrated on a chip

d) useless gates because XOR gates are the most im

portant

e) are logically equivalent

 

15. Cache memory speeds up main memory access becau

se programs have:

a) temporal and spatial locality

b) RISC instructions

c) CISC instructions

d) set-associative memory characteristics

e) local variable frames

 

16. An area of memory that is used for local variab

les and parameters is called the:

a) constant pool

b) method area

c) micro-operation ROM

d) local stack frame

e) register store

 

17. Each ISA level instruction causes:

a) two numbers to be added together

b) the program counter to be always incremented by

one

c) the execution of a series of micro-operations i

n the CPU

d) the micro-operation ROM to be rewritten

e) the pipeline to be flushed

 

18. The prefetch unit has all of the following cha

racteristics EXCEPT:

a) special hardware to increment the PC

b) generally works independently of the micro inst

ruction unit

c) writes bursts of data back to memory

d) fetches instructions and places them in a shift

register

e) may need to be flushed during a program branch

 

19. A "push" operation:

a) places data on the bottom of a stack

b) places data on the top of a stack

c) places data in the middle of a stack

d) removes data from the top of a stack

e) removes data from the bottom of a stack

 

20. An external event that causes the processor to

stop its current task and jump to

another task is called:

a) a push operation

b) a bus arbitration operation

c) a starting vector address

d) an interrupt

e) a procedure call

 

21. The ISA level is the level that:

a) defines the hardware level of the CPU

b) the assembly language programmer "sees"

c) is above the Operating System level

d) defines the memory management unit

e) defines the structure of the ALU

 

22. The kernel mode of the CPU:

a) is used by typical applications programs

b) is used to produce white fluffs of starch, some

times buttered.

c) is typically used by the operating system to ex

ecute privileged instructions

d) is less restrictive than the User mode

e) is not implemented on a Pentium II

 

23. An ISA instruction can consist of:

a) opcode, pointer and flags

b) opcode, addresses and operands

c) operand, stack frame and L2 cache

d) Sequencer, program counter & address

e) interrupts, traps and faults

 

24. The addressing mode in which the address of the

operand is

given in the instruction is:

a) based-indexed addressing

b) register addressing

c) indexed addressing

d) direct addressing

e) trap addressing

 

25. Which I/O scheme is

least

efficient ( that is, wastes CPU cycles )?

a) Programmed I/O with busy waiting (looping for

device ready)

b) Interrupt driven I/O

c) DMA I/O

d) data driven I/O

e) clock driven I/O

 

26. A page fault occurs when:

a) data becomes corrupt at the address being acc

esses

b) main memory registers are empty

c) external fragmentation occurs

d) a required page is not in memory

e) a page rips from the textbook

 

27. What is Virtual Memory?

a) a scheme to fit large programs in limited size

physical memory

b) what occurs when a page is not in memory

c) instructions on how to fix a variable length o

pcode

d) memory that self-produces machine instructions

e) a scheme that limits the length (size) of segm

ents in physical memory

 

28. In a paged virtual addressing scheme, the physi

cal address space

a) is the (logical) address space of your program

b) is not broken into pages

c) is not needed

d) contains the actual code and data of your (rema

pped) process

e) can be fragmented into various sized pages

 

29. The "working set" is:

a) the most useful set of CPU registers

b) the most useful set of micro-code registers

c) the set of pages most likely to be replaced dur

ing a page fault

d) the most actively used pages of the process at

a given time

e) the most useful building blocks of the computer

system

 

30. Dynamic Link Libraries (.dll's ) :

a) are used to attach useful functions to your ap

plication program

b) can make your executable program much bigger t

han needed

c) cannot be shared by other programs

d) do not have to be linked to your program

e) are an old idea in computing and not used in W

indows 98

 

31. A "cache hit" occurs when:

a) the contents of the tag field and memory addres

s DO NOT match

b) a line entry is removed from cache and replaced

with one from memory

c) the contents of th tag field and memory address

match

d) two cache lines collide

e) the cache mob decides that an address needs to

be "eliminated"

 

32. Which of the following best describes fine grai

ned parallelism:

a) instruction level pipelining with low speed con

nections

b) multiple independent processes running on separ

ate processors

c) independent processors with no connections

d) multiple tightly coupled programs that communic

ate

e) the oak machine built from wood

 

33. In immediate addressing, the:

a) address of the operand is given in the instruct

ion

b) operand is located in a register

c) operand is contained in the instruction

d) operand is in the ozone

e) the address is given in the base register

 

34. Which type of memory has tracks and sectors?

a) cache

b) magnetic disks

c) tape

d) main memory

e) registers

 

35. Multi-computers are:

a) multiple computers physically stacked on each o

ther with a monitor

b) CPUs with private memory and an interconnection

network

c) CPUs connected with a single bus

d) computers with no memory

e) computers with multi-media options

 

36. Which is the fastest memory?

a) cache

b) hard drive

c) registers

d) ROM memory

e) optical disk

37. What can you do if your program needs 64Meg to

run and your computer has only

 

32Meg:

a) get more RAM

b) break program into pieces

c) use a virtual memory system

d) run on a computer with 128Meg of RAM

e) all of the above

(Look this answer up in the book, this question wil

l not be on the real final)

 

38. With a two-pass assembler, pass one is used to

build up a symbol table that holds:

a) labels

b) literals

c) identifiers

d) all of the above

e) none of the above

 

39. In a non-virtual memory system, when the stack

and the data/program areas in

memory collide, what happens?

a) nothing, this is normal

b) the program crashes or you get an error message

c) the CPU turns on the virtual memory system

d) you are rewarded with a big bonus for your effo

rts

e) the memory chips blowup

 

40. Language translation can be performed by the:

a) address bus

b) a C++ compiler

c) data register

d) MMU

e) data flow system

 

41. The software that manages all of the resources

of a computer system is the:

a) processor manager

b) operating system

c) Netscape Navigator

d) logic gates

e) program counter

42. The data path consists of:

a) registers, buses, ALU and shifters

b) registers, PCI cards, ISA cards and hard drives

c) the sun, moon and stars

d) RAM, ROM and flash memory

e) MMU, registers, and cache

 

43. Which of the following is not a network topolog

y:

a) tree

b) grid

c) flower

d) torus

e) ring

 

44. Which type of computer uses vector processing?

a) Cray-1

b) DEC Alpha

c) Intel Pentium III

d) ENIAC

e) Apple Powerbook

 

45. The path length is the number of clock cycles

needed to execute a set of operations.

Which is NOT a method used to shorten the cycle:

a) use a 3 bus architecture

b) overlap instructions

c) use an instruction fetch unit

d) use an universal serial bus

e) pipeline the datapath

 

46. All gates have (at least) 2 inputs except:

a) nand

b) nor

c) xor

d) inverter

e) or

 

47. Which topology is the best design for a networ

k consisting of 8 outer nodes and 1

central node:

a) Ring

b) Cube

c) Star

d) Tree

e) Grid

 

48. What does a bus arbitrator do?

a) breaks up fights and escorts kids acros

s the street

b) supplies power to the CPU

c) decides what device gets to use the bus

at that given time

d) speeds up the ALU

e) configures the OS

 

49. What type of instruction length does the Penti

um 4 use?

a) variable

b) infinite

c) fixed

d) static

e) bilateral

 

50. The CPU (Central Processing Unit) consists of:

a) Arithmetic Logic Unit, Main memory, and I/O dev

ices

b) Operating system, L2 Cache, and the Control Uni

t

c) ALU, Registers, Control Unit

d) Sectors, tracks, and cells

e) RISC registers, program counter, Superscalar Ar

chitecture