Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 08 Jan 2018 My Price 5.00

odd-parity generator

Design a controller for an odd-parity generator. The circuit should transmit 7 bits from a shift register onto the output X. Then, on the next clock cycle, the eighth value of X should be chosen to make the number of 1’s be odd. In other words, the last value of X should be 1 if there was an even number of 1’s in the shift register, so that the 8-bit output word will have odd parity. (Parity was discussed in Section 13.1.) The circuit is shown. K will be 1 when the counter reaches 111.

(a) Give the state graph for the control circuit. Assume St = 1 for one clock cycle (three states).

(b) Implement the controller using D flip-flops and any necessary gates. Use a one-hot state assignment.

 

 

 

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Maurice Tutor
(5)
Status NEW Posted 08 Jan 2018 03:01 PM My Price 5.00

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