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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
The circuit of Fig. P6.13a contains a JK flip-flop and a D flip-flop. Complete the timing diagram of Fig. P6.13b by drawing the waveforms of signals Q1. and Q2, assuming that:
(a) The 1K flip-flop is negative edge triggered.
(b) The 1K flip-flop has data lockout.

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