A 4-bit up/down binary counter with output Q works as follows: All state changes occur on the rising edge of the CLK input, except the asynchronous clear (ClrN). When ClrN = 0, the counter is reset regardless of the values of the other inputs.

If the LOAD input is 0, the data input D is loaded into the counter.

If LOAD = ENT = ENP = UP = 1, the counter is incremented.

If LOAD = ENT = ENP = 1 and UP = 0, the counter is decremented.

If ENT = UP = 1, the carry output (CO) = 1 when the counter is in state 15.

If ENT = 1 and UP = 0, the carry output (CO) = 1 when the counter is in state 0.

(a) Write a VHDL description of the counter.

(b) Draw a block diagram and write a VHDL description of an 8-bit binary up/ down counter that uses two of these 4-bit counters.