Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Management Posted 24 Jan 2018 My Price 7.00

enhancement-type MOS transistors

The enhancement-type MOS transistors have the following parameters:

For a CMOS complex gate OAI432 with (W/L)p = 30 and (W/L)n = 40,

(a) Calculate the WIL sizes of an equivalent inverter with the weakest pull-down and pull-up. Such an inverter can be used to calculate worst-case pullup and pull-down delays, with proper incorporation of parasitic capacitances at internal nodes into the total load capacitance. In this problem, you are asked to calculate only (W/L)worse case for both p-channel and n-channel MOSFETs by neglecting the parasitic capacitances.

(b) Do the layout of OAI432 with minimal diffusion breaks to reduce the number of polysilicon column pitches. With proper ordering of polysilicon gate columns, the number of diffusion breaks can be minimized. One way of achieving such a goal is to find a Euler path common to both p-channel and n-channel nets using graph models. Symbolic layout that shows source and drain connections is sufficient to answer this problem.

 

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Maurice Tutor
(5)
Status NEW Posted 24 Jan 2018 09:01 PM My Price 7.00

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