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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
14.67 A particular logic gate has tPLH and tPHL of 30 ns and 50 ns, respectively, and dissipates 1 mW with output low and 0.6 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation).
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