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MBA IT, Mater in Science and Technology
Devry
Jul-1996 - Jul-2000
Professor
Devry University
Mar-2010 - Oct-2016
For my CS M51A class. Solve all the problems according to the instructions.
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CS M51A / EE M16Winter 2016Homework #5Problem 1:Implement the following program repeatedly using a single 8-bitadder/subtracter (AS) module, 8-bit registers, as few as possible as small as possiblecounters and combinational modules of your choice.The AS module executes addition, when control signal c1 is 0 and subtraction whencontrol signal c1 is 1. Every five cycles the 7-bit input variables b, c, and e are updatedwith new values. All values (given and calculated) are positive. Values a, f, g, h, and dshould be available one each clock cycle, in their respective order.statement 1. a = b + c;statement 2. f = b + e;statement 3. g = a − c;statement 4. h = b + e;statement 5. d = b − c;Problem 2:Using modulo 16 counters and multiplexers implement a system thatproduces the following sequence:Problem 3:Design a system which outputs 1 if 4 of the last 5 characters are 1011 with atmost 2 mismatched bits. The definition of mismatched bit is a bit in the sequence whichdoesn’t correspond the its specified value. For example, for pattern 1111, the followingsequences have 1 mismatched bit 0111, 1011, 1101, 1110. Use shift registers andminimal number of as small as possible multiplexers.Problem 4:Using one 2-bit comparator module, design a system that sorts twelve 4-bitnumbers. What is the minimal number of required clock cycles for your design tocomplete this task.Problem 5:Four four-bit numbers (a, b, c, and d) and input signal x are given. Design asystem which produces the sum of the two largest numbers if x = 0, and produces the sum
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