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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
We wish to design a decoder, with three inputs, x, y, z, and eight active high outputs, labeled 0 , 1 , 2 , 3, 4 , 5 , 6 , 7. There is no enable input required. (For example, if xyz 011, then output 3 would be 1 and all other outputs would be 0.)
The only building block is a two-input, four-output decoder (with an active high enable), the truth table for which is shown below

Draw a block diagram of the system using as many of these building blocks as are needed.
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