Maurice Tutor

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    Argosy University/ Phoniex University/
    Nov-2005 - Oct-2011

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    Phoniex University
    Oct-2001 - Nov-2016

Category > Computer Science Posted 27 Jul 2017 My Price 6.00

CMOS logic fashion

Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors:

2. Consider the circuit of Figure 6.1.

What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8.

b. What are the input patterns that give the worst case tpHL and tpLH. State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes.

c. Verify part (b) with SPICE. Assume all transistors have minimum gate length (0.25mm).

 

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Maurice Tutor
(5)
Status NEW Posted 27 Jul 2017 03:07 PM My Price 6.00

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