Design a controller for the circuit of Problem 12.39 that will add three numbers. Assume each number (including the first one) appears on the 8-bit input data line for two consecutive clock cycles. You may not assume that the registers begin with a value of 0. When St = 1, the first input appears on the input data line for that clock cycle and the next one. The circuit should halt when the answer goes into the accumulator, and output a signal Done = 1. Done should remain 1 until St returns to 0. You may assume St = 1 for enough time for the operation to complete. Give the block diagram and the state graph (seven states), but you do not need to implement the state graph.

Problem 12.39

When an adder is part of a larger digital system, an arrangement like the given figure often works well. For the control signals and the input data in the following table, give the value of the addend, the accumulator, and the bus at the end of each clock cycle (i.e., immediately before the active clock edge). Express the register and bus values in decimal.