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bachelor in business administration
Polytechnic State University Sanluis
Jan-2006 - Nov-2010
CPA
Polytechnic State University
Jan-2012 - Nov-2016
Professor
Harvard Square Academy (HS2)
Mar-2012 - Present
Design a sequential circuit having one input and one output that will produce an output of 1 for every second 0 it receives and for every second 1 it receives.

(a) Design a Mealy sequential circuit using D flip-flops, showing a reduced state graph, and equations for the output and D inputs. It should be a reasonably economical design.
(b) Repeat part (a) for J-K flip-flops.
(c) Design a Moore sequential circuit using T flip-flops to do the same task, showing a state graph and input equations for a reasonably economical design.
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