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Category > Computer Science Posted 05 May 2017 My Price 6.00

The path from the data cache to the register file


The path from the data cache to the register file of a microprocessor involves 500 ps of gate delay and 500 ps of wire delay along a repeated wire. The chip is scaled using constant field scaling and reduced height wires to a new generation with S = 2. Estimate the gate and wire delays of the path. By how much did the overall delay improve?

 

 

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Alpha Geek
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Status NEW Posted 05 May 2017 03:05 PM My Price 6.00

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