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MCS,PHD
Argosy University/ Phoniex University/
Nov-2005 - Oct-2011
Professor
Phoniex University
Oct-2001 - Nov-2016
A sequential circuit is shown in Figure 29. The timing parameters for the gates and flip-flops are as follows:

(a) Find the longest path delay from an external circuit input passing through gates only to an external circuit output.
b) Find the longest path delay in the circuit from an external input to positive clock edge.
(c) Find the longest path delay from positive clock edge to output.
(d) Find the longest path delay from positive clock edge to positive clock edge.
(e) Determine the maximum frequency of operation of the circuit in megahertz (MHz).

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